Submicron SRAM experiences performance problems in 20 nm and below process technologies due to the increased parasitic capacitances and resistances of bit lines. The increased parasitic effects degrade the slope of the bit lines during write operations, thereby increasing the cycle times for writing data to SRAM memory cells. However, increasing the size of write drivers for the bit lines fails to improve the slope of the bit line during logical state transitions because the current capabilities of the write drivers tend to saturate even as the size of the drivers are increased.